1. Field of the Invention
The present invention relates to the field of integrated circuit packaging and technology.
2. Background Art
An integrated circuit (IC) is a microelectronic semiconductor device consisting of many interconnected transistors and other components. ICs are generally fabricated on one or more small rectangles cut from a semiconductor material, such as silicon. A multilayer IC generally consists of one or more signal routing layers separated by metal planes for power and ground. This multilayer arrangement is named a multilayer laminate package.
Multilayer laminate packages are subject to a problem called xe2x80x9ccrosstalkxe2x80x9d due to the nature of their construction. Before further discussing the problems associated with crosstalk, a typical multilayer laminate package is described below.
FIG. 1 illustrates a typical multilayer laminate package configuration 100. Signal routing layer 120 is in contact with ground layer 110 and Vcc layer 130. Signal routing layer 120 has a plurality of trace routing lines that connect the pins of the package to the semiconductor die. The construction and use of these components is well known to those of skill in the art. Ground layer 110 is dedicated to full system ground and chassis ground. Vcc layer 130 is in contact with signal routing layer 140. Vcc layer 130 carries voltage signal Vcc to the components on signal routing layer 120 and signal routing layer 140. Signal routing layer is in connection with ground layer 150. Thus, multilayer laminate packages are designed so that multiple signal routing layers are sandwiched between ground planes and Vcc planes. The signal routing traces are composed of segments oriented at zero degrees, forty-five degrees, ninety degrees and one-hundred-and-thirty-five degrees to any edge of the package.
For reasons relating to the manufacturing process, Vcc layer 130 and ground layer 110 generally need to have a perforated mesh pattern. The mesh size is large compared to the width of the traces used for routing signals. For example, typical dimensions currently used are twenty to fifty microns for the signal trace width, and one-hundred-and-fifty to four-hundred microns for of the mesh openings. The mesh planes are laid out on a grid and that grid usually follows a vertical-horizontal direction.
A major consideration in multilayer laminate package design is the minimization of crosstalk. Crosstalk refers to interference between signal routing lines. It is undesirable because it contributes to errors on the signals propagated in the traces. Crosstalk is due to electromagnetic (inductive) or electrostatic (capacitive) coupling between the conductors carrying the signals. The longer two or more parallel signal traces run together, the higher the crosstalk is as between those lines. Also, crosstalk is directly proportional to the distance between signal traces. Crosstalk between adjacent traces on the same layer is the dominant crosstalk contribution in a package. This coupling is very strongly influenced by the presence of a solid plane above or below. Studies have shown that crosstalk between traces with no plane can be three to ten times higher than otherwise.
Crosstalk can be reduced by shielding the signal trace lines from one another and increasing the distance between them. Thus, in a typical multilayer IC configuration, the signal trace lines on adjacent signal routing layers are insulated by the mesh layer sandwiched between these planes. Thus, crosstalk between adjacent signal routing layers is a lesser problem. When groups of signals traverse multiple mesh openings, the crosstalk between traces on different layers also increases significantly due to the absence of a solid plane between them. This is also a cross talk issue in electronic package design that arises from the use of mesh planes.
The usual technique of minimizing package crosstalk is to push the package substrate design rules to minimize the diameter of the mesh openings in the solid planes. This involves tweaking the package manufacturing process to minimize the impact of reduced adhesion of various layers in the package and requires a requalification of certain aspects of the package. These tests include the use of thermal cycling to check integrity. Very often, the tradeoff results in a compromise between package reliability criteria and the level of induced crosstalk.
Furthermore, the insertion of mesh openings on the Vcc and ground layers is a postprocessing step in package fabrication. The placement of perforations into a conducting layer is decided after the first design of the package. Therefore, the package design must necessarily be reviewed and modified to mitigate the most extreme cases of groups of signal trace lines traversing mesh openings. The prior art crosstalk minimization method lengthens the package design process. Further, package redesign and subsequent retesting significantly add to the project cost.
The present invention is a technique to minimize crosstalk in multilayer IC packages. According to one or more embodiments of the present invention one or more signal routing layers are separated by planes for power and ground. Signal trace routing on the routing layers follows either horizontal (0 degrees), vertical (90 degrees) or diagonal (45 and 135 degrees) directions for obtaining high routing densities in the package as is the present design practice.
The power and ground planes in one embodiment of the present invention are constructed as a mesh having numerous perforations. The directionality of the mesh pattern is set diagonally to the horizontal and vertical axes. In one embodiment, the axes of the perforations follow a 30 degree-120 degree orientation. In another embodiment, the axes of the perforations are set to follow a 60 degree-150 degree orientation. By setting the orientation of the mesh to follow either diagonal, it is guaranteed that the number of mesh openings that any given set of three traces encounters is reduced by at least a factor of two. Thus the present invention reduces crosstalk in the package by approximately 50%.
Since the insertion of mesh openings is an automated post-processing step, the implementation of the present invention requires only a modification of design software. Therefore, the invention does not increase the total cost of the package.